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Eduqas GCSE Systems Architecture – Learn Guide

The purpose of the CPU – Eduqas GCSE Systems Architecture Sample Lesson

1.1 What is the CPU?

1.2 The cycle in outline

1.3 Practice: the purpose of the CPU

CPU components – Eduqas GCSE Systems Architecture

2.1 The ALU and the control unit

2.2 Cache and registers

2.3 Practice: CPU components

Von Neumann architecture – Eduqas GCSE Systems Architecture

3.1 The stored program concept

3.2 PC, MAR, MDR and accumulator

3.3 Practice: von Neumann registers

The fetch-decode-execute cycle – Eduqas GCSE Systems Architecture

4.1 The fetch stage

4.2 Decode and execute

4.3 Practice: the FDE cycle

The CIR and the full cycle – Eduqas GCSE Systems Architecture

5.1 The current instruction register

5.2 Practice: all five registers

CPU performance – Eduqas GCSE Systems Architecture

6.1 Clock speed

6.2 Cache size and cores

6.3 Practice: CPU performance

6.4 Levels of cache

Additional hardware – Eduqas GCSE Systems Architecture

7.1 Motherboards and GPUs

7.2 Sound cards

7.3 Practice: additional hardware

Embedded systems – Eduqas GCSE Systems Architecture

8.1 What is an embedded system?

8.2 Characteristics of embedded systems

8.3 Practice: embedded systems

Bringing it together – Eduqas GCSE Systems Architecture

9.1 Mixed retrieval

9.2 Exam practice

5.2 Practice: all five registers

Eduqas GCSE Systems Architecture – Learn Guide
The CIR and the full cycle – Eduqas GCSE Systems Architecture
5.2 Practice: all five registers

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